1. Field of the Invention
This invention relates to an etching method to planarize the surface shape of a wafer, and an etching device employing this method.
2. Description of the Related Art
The rising integration levels in semiconductor devices in recent years have been accompanied by advances in the miniaturization and multilayer design of elements and wiring. Pattern formation for fine wiring may also rely on thin film fabrication techniques and lithography, but with the adoption of multilayer designs, a planarized base surface is indispensable for the precise formation of fine patterns.
For example, in reducing the size of a gate electrode, much depends on the performance of the exposure equipment used in lithography processes; however where miniaturization of device isolation regions and reduction of distances from other gate electrodes are concerned, techniques to planarize the base surface using shallow trench isolation (hereafter abbreviated “STI”) are also attracting attention in addition to advanced lithographic techniques.
FIGS. 1A to 1C shows cross-sectional process diagrams of STI processes, as one example of a planarizing process. As shown in FIG. 1A, in an STI process, first a stopper layer 3 made of silicon nitride is patterned via a thermal oxide film 2 on the wafer 1 which is the silicon substrate, and this stopper layer 3 is used as an inorganic mask to form trenches 4 on the surface side of the wafer 1. Then, a buried insulating film 5 of silicon oxide is deposited so as to bury these trenches 4. Here, the buried insulating film 5 is formed by ordinary CVD; however when using CVD for film deposition, dispersion occurs in the deposited film thickness at the surface of the wafer 1, so that an insulating film is formed in which, compared for example with the thickness t1 at the center of the wafer 1, the film thickness t2 at the periphery is larger.
In this state, if CMP (chemical-mechanical polishing) is performed to planarize the buried insulating film 5, a global step existing at the surface of the initial buried insulating film 5 remains at the surface of the buried insulating film 5 even after polishing.
Hence as shown in FIG. 1B, as preprocessing for planarizing by CMP, etching is performed in order to render the thickness of the buried insulating film 5 uniform. In this etching, the film thickness profile of the buried insulating film 5 which is the film to be etched is ascertained in advance, and etchant liquid is discharged only at thick portions of the buried insulating film 5 to etch the buried insulating film 5. In this case, as for example shown in FIG. 2, the discharge position of the etchant liquid L1 is caused to move in the radial direction of the rotating wafer 1. At this time, the discharge position of the etchant liquid L1 is moved such that the etchant liquid L1 is supplied in greater total quantities to portions of the film that are thick, based on the film thickness profile information in the radial direction of the wafer 1 for the film to be etched (the buried insulating film 5), as shown by the film thickness profile of FIG. 3A.
Accordingly, buried insulating film the thickness of which is greater at the periphery of the silicon substrate than at the center (0) becomes such that the film thickness at the periphery and near the center (0) is the same, as shown by the profile of FIG. 3B, so that a globally planarized buried insulating film on the silicon substrate is obtained (see Japanese Patent Laid-open No. 2002-134466).
Further, in STI formation, when by the above-described etching the thickness of the buried insulating film 5 is rendered uniform as shown in FIG. 1B, CMP of the surface of the buried insulating film 5 is performed until the stopper layer 3 is exposed, as shown in FIG. 1C. Accordingly, excessive polishing at the center of the wafer 1 can be prevented without leaving buried insulating film 5 on the stopper layer 3 at the periphery of the wafer 1.
However, when using the above-described etching method, the film thickness profiles of the film for processing which can be corrected are limited; for example, the film thickness of a film for processing with a large film thickness near the center (0) of the wafer, as shown in FIG. 4A, cannot be rendered uniform. That is, if a film for processing having such a film thickness profile is subjected to correction of film thickness using the above-described etching method, the discharge position of the etchant liquid 1 is positioned near the center (0) of the wafer, where the film thickness is greatest, so that the etchant liquid L1 flows toward the wafer periphery due to centrifugal force and is supplied to the entire surface of the wafer. Hence even if such an etching method is used, the entirety of the film for processing is merely etched to become a thin film, as shown in FIG. 4B, and the film thickness cannot be rendered uniform.
In the STI formation process, planarizing by CMP is performed on the buried insulating film (film for processing) subjected to such etching. Consequently, as shown in FIG. 5A, if the CMP conditions are set so as to expose the stopper layer 3 at the wafer periphery, the buried insulating film 5 on the stopper layer 3 at the center of the wafer remains in place and is not polished. If this state is retained in the next process, and an attempt is made to remove the stopper layer 3 by wet etching using hot phosphoric acid or by isotropic chemical dry etching, the remaining buried insulating film 5 at the wafer periphery acts as a mask, and complete removal is not possible. As a result, the desired etched shape is not obtained at the wafer periphery, leading to unsatisfactory semiconductor device characteristics and drops in production yield.
Further, if in order to avoid the above adverse effects CMP polishing is performed so as to expose the stopper layer 3 at the center of the wafer as shown in FIG. 5B, the buried insulating film 5 in the trenches 4 is polished excessively at the wafer periphery, so that the thickness of the buried insulating film 5 in the trenches 4 is different at the wafer center and at the periphery. As a result, the element isolation characteristics are different across the wafer surface. Hence the desired semiconductor device characteristics are not obtained, and drops in production yield result.
In light of the above, this invention has as an object of providing an etching method and etching device, in which the film thickness of a film to be processed having any film thickness profile can be uniform, regardless of the film thickness profile of the film to be processed on the wafer, and global planarizing of the wafer surface can be obtained.